1. Field of the Invention
The present invention relates to a data communications circuit; and more particularly, to a circuit and method for clock and data recovery in high speed digital communications via optical fiber or wire connection.
2. Description of the Prior Art
Present telecommunications and computer systems require the high data-rate transmission of digital information between different circuits. These circuits may be in close proximity, such as within a single equipment cabinet, or they may be separated by very long distances. Data may be transmitted either by electrical impulses carried using a wired connection such as a coaxial cable or a conductive trace on a circuit board or as light pulses transmitted through optical fibers. Light pulses are generally generated by laser diodes (LD's) or light emitting diodes (LED's) and injected into long fibers of glass or polymeric materials. The fibers are capable of propagating the light with extremely low losses and acceptably low dispersion, whereby information embodied in the modulation pattern may be conveyed. The light that emerges from the other end of the fiber can be detected and reconverted into electronic signals that reproduce the original signal. In most cases, a single connection is used in both optical and electrical systems and there is no provision for transmitting a separate clock signal. The increasingly high data rates now being used in digital systems impose stringent requirements if an acceptably low bit error rate (BER) is to be attained.
Transmission of digital data, whether done electrically or optically, generally employs one of two formats: return-to-zero (RZ) format or non-return-to-zero (NRZ) format. In both formats, a specific time interval is allocated for each bit. In RZ format, every binary 1 is represented by a full transition (low→high→low) between signal levels, and every binary 0 represented by the absence of any pulse transition. In NRZ format, each binary 1 or 0 bit is represented by a signal level that remains high or low, respectively, during the bit's entire time period, which is given by the reciprocal of the data rate. Transitions (high→low or low→high) occur only when successive bits are different; there are no transitions between two successive like bits. NRZ format is generally preferred, because it inherently permits a greater data rate (about double) for a given frequency bandwidth in the communications channel.
The timing of the bits of digital data transmitted in either RZ or NRZ format is referenced to a system clock at the origin. The timing ordinarily is not transmitted downstream using a separate clock signal, so it must be recovered at the destination in order to properly interpret the received bit stream. The process of recovering the clock and data is typically termed clock data recovery (CDR). NRZ format typically presents a greater difficulty, because fewer transitions are available from which to recover the clock. Suitable CDR methods are clearly essential for digital communications circuits and systems for a wide variety of systems for data transmission, whether over short distances within a piece of equipment (e.g. communication with a disk drive of a computer system) or for extended distances for telecommunications or computer networking.
The problem of clock recovery is particularly challenging in high-speed, burst mode communications, by which is meant a situation in which a relatively large amount of information is transmitted during a transmission interval, followed by a quiescent interval of indeterminate duration. The desirability of burst-mode transmission arises in many data communications situations. While certain known CDR circuits function acceptably well with an extended, if not continuous, data stream, burst-mode transmission presents far greater difficulties. The timing signal needs to be established quickly as each burst begins, and it must be re-acquired for each subsequent burst.
Many conventional CDR circuits employ a phase lock loop (PLL) circuit operating on the incoming data to provide a local clock signal synchronized to the rate of the incoming data. One such PLL CDR circuit is depicted by FIG. 1. However, PLL circuits, including that of FIG. 1, ordinarily require a relatively long time to settle before they are properly synchronized. Accurate clock recovery and data extraction are only possible after that synchronization is achieved.
A further difficulty is that the signals encountered in data communications are not simple sine waves or modulated sine waves, in which there is substantial harmonic content at the base frequency. Although synchronized to an underlying clock that is provided at the source and has a well-defined base frequency, the data stream is an apparently random signal. Little of the actual spectral energy density in the data stream is at the base frequency. Instead, a data stream, particularly one in NRZ format, has a relatively broadband spectrum, in contrast to the relatively narrow bandwidth of the data commonly encountered by PLLs in synthesizers, demodulators, and modulators.
The settling time required for a conventional PLL-based CDR circuit is frequently accommodated by appending a relatively long header to the essential data. The header provides enough time for the CDR circuit to settle, after which it can reliably process the incoming data stream.
The addition of a header of such length has little impact on overall transmission efficiency for data provided in extended transmissions. On the other hand, in burst mode, if the required header is an appreciable fraction of the overall amount of actual data within each burst, transmission overhead increases and effective throughput is reduced. In many situations, such as computer networking, a single communications line is appointed to service multiple recipients of data from different sources. Over a long time, each recipient often requires only a small portion of the total available bandwidth, but still desires frequent and data-intensive rapid responses for short, randomly occurring periods. In such instances, it is highly desirable to minimize the amount of unneeded transmission overhead to maximize the effective overall capacity of the data line.
One common data transfer protocol using high-speed, burst mode communications is the GPON system, which operates with a data rate tightly controlled to be 1.25 gigabits per second (Gbps). A typical PLL CDR circuit used with a 1.25 Gbps system requires a time on the order of 25-500 ns to settle, depending on the particular design of the system used.
As a result of continuing increases in demands for high bandwidth digital data transmission, especially for burst-mode communications, there remains a desire and need for improved data communications circuits, notably including improved clock data recovery circuits.